High resolution phase frequency detectors

ABSTRACT

An inexpensive and reliable, high resolution digital phase detector for timing circuits for wireless, optical or wire-line transmission systems. In particular this invention allows using size limited clock counters for measurements of unlimited time ranges by combining unlimited number of intermediate samples without accumulating samples granularity errors. In addition to the measurements of the final time ranges, the intermediate samples are available for purposes of digital signal processing.

This application is a 371 of PCT/CA01/00723 filed May 24, 2001 andclaims benefit of provisional application 60/206,579 filed May 24, 2000.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention is directed to providing high resolution low cost digitalphase detectors which can be used in digital phase locked loops (DPLLs)and shall also make possible other replacements of analog circuits bytheir digital implementations.

The high resolution phase detectors (HRPD) can be used for a wide rangeof data rates, and for wireless, optical, or wireline transmission andcommunication systems.

2. Background Art

Most of currently used digital phase detectors have resolution limitedby a clock cycle time. While some most advanced digital phase detectorsallow higher resolutions which are comparable with propagation delays ofclock propagating gates, they have other limitations such as: complexalgorithms which are conditioned by propagation delays of detectortiming circuits, and dependency of their phase resolution ontechnological process and power supply variations.

The closest background solution is presented by Bogdan (U.S. Pat. No.6,148,052). However this background solution requires additionaloscillator circuit implemented with free running ring oscillator havingunknown oscillation frequencies dependent on IC process deviations andpower supply variations causing propagation delays deviations rangingfrom −50% to +50%.

Outputs of such additional unpredictable oscillator circuit are used tocapture a phase of a first signal frame and a phase of a second signalframe, which need to be subtracted from each other to calculate a phaseskew between the first signal frame and the second signal frame.Therefore in addition to the oscillator circuit, said backgroundsolution requires:

-   -   separate circuits for capturing first signal phase with        oscillator outputs while other circuits are used for capturing        second signal phase with the oscillator outputs;    -   additional circuits for subtracting such separately captured        first signal phase from second signal phase;    -   oscillator calibration circuits for counting and capturing        oscillator outputs over a predetermined fixed time period;    -   control unit circuits and subroutines for processing and using        the above calibration results for recalculating the above        mentioned inter-signal phase skews.

There is a need for digital phase detectors which have simpleralgorithms and greater independence versus the propagation delays of thedetector timing circuits and the clock propagating gates.

Such much simpler digital phase detectors are provided by the presentinvention which eliminates the additional free running oscillator andthe above mentioned additional circuits and calibration relatedsubroutines. These improvements are achieved by changing principle ofoperation, as the present invention:

Propagates the first signal clock through serially connected gates anduses outputs of these gates for sensing phase of the second signal orpropagates the second signal through serially connected gates and usesoutputs of these gates for sensing phase of the first signal clock,instead of using outputs of the additional free running oscillator forcapturing phases of the first signal and the second signal.

Since the first signal and the second signal are much more stable thanthe free running oscillator; the above calibration circuits are replacedby much simpler self-calibration means or by stabilizing propagationdelays of the serially connected gates with phase locked loops or withdelay locked loops.

BRIEF SUMMARY OF THE INVENTION

It is an object of present invention to provide digital high resolutionphase detectors which are simple and reliable and can be used in varietyof communication systems.

Variety of the high resolution phase detectors are described in thisdocument using the same terms which are explained below.

First signal clock f_(F1) is a higher frequency signal which is used tomeasure time periods corresponding to single or multiple cycles of alower frequency signal which is called second signal frame fr_(S2).

High resolution phase detectors comprise:

-   -   a counter and a buffer configuration for counting the first        signal clock during every frame of a second signal, and for        buffering the counted value until it is read by a phase        processing unit;    -   a high resolution extension of the counter and buffer        configuration, which measures a remainder of a frame phase skew        which is lesser than one clock cycle;    -   a detector timing circuit for synchronizing the clock counting        and the buffer reading versus the signal frame related phase        capture into a phase capture register;    -   a high resolution phase processing method for combining contents        of the clock counter and the phase capture register into a high        resolution phase measurement.

The high resolution extension can be implemented by using a propagationcircuit and a phase capture register, as it is explained below.

The first signal clock or the measured second signal frame is propagatedthrough multiple serially connected gates.

The first signal clock or the second signal frame is captured in thephase capture register by the outputs of the serially connected gates,or the outputs of the serially connected gates are captured in the phasecapture register by the first signal clock or by the second signalframe. The content of the phase capture register is used to calculate aphase skew of the second signal frame versus the first signal clock.

The high resolution phase processing method comprises:

-   -   a calculation of an approximate phase error between the first        signal and the second signal, by subtracting a number of first        signal clock cycles which corresponds to zero phase skew of the        second signal frame, from a last number of clock cycles which        has been read from the buffer;    -   a calculation of a high resolution phase error by adding the        high resolution extension to the approximate phase error;    -   elimination of phase error accumulations for multiple        measurements, by subtracting last high resolution extension from        a period of the first signal clock, and by adding the resulting        remainder of the clock cycle to an adjacent phase error        measurement.

The above methods allow designing multiple different implementations ofHRPD.

Some of these HRPD implementations are defined in the GENERALDESCRIPTION OF THE INVENTION and are shown with more details in theDESCRIPTION OF THE PREFERRED EMBODIMENTS.

BRIEF DESCRIPTION OF THE DRAWINGS

HRPD implementation and preferred embodiments of the invention will nowbe described with reference to attached drawings in which:

FIG. 1 shows Circuits of the HRPD Config.1 based on an open ended delayline captured by frame edge.

FIG. 2 shows timing analysis of the HRPD Config.1.

FIG. 3 shows High Resolution Extension of the HRPD Config.2 based on aring oscillator captured by frame edge.

FIG. 4 shows High Resolution Extension of the HRPD Config.3 based onclock signal captured by frame delay line edges.

FIG. 5 shows Detector Timing Circuit of the HRPD Config.3, which solvesmost critical timing of the HRPD Config.3.

FIG. 6 shows Timing Analysis of the HRPD Config.3.

FIG. 7 shows High Resolution Extension of the HRPD Config.4 based onframe delay line captured by clock signal.

FIG. 8 shows Detector Timing Circuit of the HRPD Config.4, while

FIG. 9 shows resulting Timing Analysis of the HRPD Config.4.

FIG. 10 shows High Resolution Extension of the HRPD Config.5 based onframe captured by clock delay line.

FIG. 11 shows Detector Timing Circuit of the HRPD Config.5, while

FIG. 12 shows resulting Timing Analysis of the HRPD Config.5.

FIG. 13 shows High Resolution Extension of the HRPD Config.6 based onframe captured by ring oscillator, while

FIG. 14 shows resulting Timing Analysis of the HRPD Config.6.

GENERAL DESCRIPTION OF THE INVENTION

1. HRPD Config.1 based on delay line captured by frame edge

The HRPD Config.1 uses:

-   -   an open ended delay line which is built with multiple serially        connected gates, which the first signal clock is continuously        propagated through;    -   a leading edge of the second signal frame to capture a status of        the outputs of the delay line in the phase capture register;    -   a calibration method of gates propagation delays, which is based        on capturing the whole cycle of the first signal clock as it is        propagated along the delay line and dividing the first signal        cycle time by the number of gates which carried the whole cycle        propagation.

The calibration method comprises:

-   -   statistical averaging of the calibration result, in order to        eliminate most of a granularity error caused by capturing of the        integer gates number and to reduce an error caused by power        supply ripple.

The calibration method can further comprise a reduction of an errorcaused by an occurrence of different gate delays at the end versus thefront of the delay line:

-   -   by assigning higher weights to the cycle gate number, if        captured cycle propagating gates are located at the front of the        delay line;    -   by using the weighted cycle gate numbers for the statistical        averaging of the calibration result.

2. HRPD Config.2 based on ring oscillator captured by frame edge.

The HRPD Config.2 uses:

-   -   the signal propagation circuit which is built with multiple        serially connected gates forming a ring oscillator which is        phase locked to the first signal clock;    -   a leading edge of the second signal frame to capture a status of        the outputs of the ring oscillator gates in the phase capture        register.

Since the number of ring oscillator gates and the first signal clockperiod are known, calibration of gates propagation delay is not neededfor the HRPD Config.2.

3. HRPD Config.3 based on clock signal captured by frame delay lineedges.

The HRPD Config.3 uses:

-   -   the signal propagation circuit which is built with multiple        serially connected gates forming an open ended delay line, which        the second signal frame is continuously propagated through;    -   the outputs of the delay line gates to capture a waveform of the        first signal clock, in the phase capture register;    -   a calibration method of gates propagation delays, which is based        on capturing the whole cycle of the first signal clock as it        occurs along the inputs of the phase capture register, and        dividing the first signal cycle time by the number of the delay        line gates which outputs captured the whole clock cycle.

The calibration method comprises:

-   -   statistical averaging of the calibration result, in order to        eliminate most of a granularity error caused by having an        integer number of the capturing gates, and to reduce an error        caused by power supply ripples.

The calibration method can further comprise a reduction of an errorcaused by an occurrence of different gate delays at the end versus thefront of the delay line:

-   -   by assigning higher weights for the cycle capturing gate number,        if the cycle capturing gates are located at the front of the        delay line;    -   by using the weighted cycle gate numbers for the statistical        averaging of the calibration result.

4. HRPD Config.4 based on frame delay line captured by clock signal.

The HRPD Config.4 uses:

-   -   the signal propagation circuit which is built with multiple        serially connected gates forming an open ended delay line, which        the second signal frame is continuously propagated through;    -   the outputs of the delay line gates are captured by rising edges        of the first signal clock in phase capture registers;    -   a calibration method of gates propagation delays which is based        on capturing the frame delay line by 2 consecutive first signal        rises, and dividing the first signal cycle time by a difference        between numbers of gate delays which were captured by the        consecutive first signal rises.

The calibration method comprises:

-   -   statistical averaging of the calibration result, in order to        eliminate most of a granularity error caused by capturing an        integer number of the delay line gates, and to reduce an error        caused by power supply ripples.

The calibration method can further comprise a reduction of an errorcaused by an occurrence of different gate delays at the end versus thefront of the delay line:

-   -   by assigning higher weights to the cycle capturing gate number,        if the cycle capturing gates are located at the front of the        delay line;    -   by using the weighted cycle gate numbers for the statistical        averaging of the calibration result

5. HRPD Config.5 based on frame captured by clock delay line.

The HRPD Config.5 uses:

-   -   the signal propagation circuit which is built with multiple        serially connected gates forming an open ended delay line, which        the first signal clock is continuously propagated through;    -   the outputs of the delay line gates to capture a rise of the        second signal frame in the phase capture register;    -   a calibration method of gates propagation delays which is based        on:        -   capturing a frame rising edge by two consecutive rising            edges of the signal clock which occur simultaneously along            the delay line;        -   and dividing the first signal cycle time by a number of            delay line gates which existed between said clock edges when            they captured simultaneously the frame rising edge in the            capture register;    -   a capture synchronization method which prevents the next        propagated clock edges from overwriting said captures of the        frame rise by said two consecutive clock edges.

The calibration method comprises:

-   -   statistical averaging of the calibration result, in order to        eliminate most of a granularity error caused by having an        integer number of the capturing gates, and to reduce an error        caused by power supply ripples.

The calibration method can further comprise a reduction of an errorcaused by an occurrence of different gate delays at the end versus thefront of the delay line:

-   -   by assigning higher weights to the cycle capturing gate number,        if the cycle capturing gates are located at the front of the        delay line.    -   by using the weighted cycle gate numbers for the statistical        averaging of the calibration result

6. HRPD Config.6 based on frame captured by ring oscillator.

The HRPD Config.6 uses:

-   -   outputs of the signal propagation circuit, which is built with        multiple serially connected gates forming a ring oscillator        which is phase locked to the first signal clock;    -   the outputs of the ring oscillator gates to capture a rise of        the second signal frame in the phase capture register;    -   a capture synchronization method which prevents next propagated        clock edges from overwriting said capture of the rise of the        second signal frame.

Since the number of ring oscillator gates and the first signal clockperiod are known, calibration of gates propagation delay is not neededfor the HRPD Config.6.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

1. HRPD Config.1 based on delay line captured by frame edge

The HRPD Config.1 is shown in FIG. 1.

Approximate phase measurements are explained below.

The HRPD Config.1 uses two symmetrical phase counters buffers A/B(PCBA/PCBB), which perform reverse functions during alternative A/Bcycles of the frame signal fr_(S2). During the A cycle, the PCBA countsthe number of incoming f_(F1) clocks, but during the following B cyclethe PCBA remains frozen until its content is read by a phase processingunit (PPU), and subsequently the PCBA is reset before the beginning ofthe next A cycle. Reversibly, the PCBB performs counting during the Bcycle and is read and reset during the following A cycle.

Such symmetrical PCBA/PCBB configuration allows much more time forcounters propagation by inhibiting counting long before the actualreading takes place.

Therefore, much higher frequencies of counted clocks are allowed for thesame IC technology.

Generally speaking the above concept of a digital phase detector,represents one of several possible HRPD solutions, which are based oncounting the first signal clock during every frame of the second signal,wherein the second signal frame contains a number of the second signalclocks.

The symmetrical twin pair PCBA/PCBB configuration:

-   -   allows higher counting speeds by eliminating all problems        related to counters propagation delays.    -   allows measurements of fr_(S2) versus f_(F1) phase errors, with        a resolution of a single f_(F1) period.

When fr_(S2) rise signals the end of the current phase measurement,counting of f_(F1) clock is inhibited and the counter content remainsfrozen, until the next rise of the fr_(S2) signal when the counted clockis enabled again. The whole fr_(S2) cycle is a very long freeze period,which is more than sufficient to accommodate; any kind of counterpropagation, the counter transfer to the phase processing unit, and thecounter reset. During the freeze period a mate counter is kept enabledand provides measurement of fr_(S2) phase.

More detailed operations of the PCBA/PCBB configuration for bothalternatives STOPA=1 and STOPB=1, are further explained below.

When STOPA signal is active, HRPD circuits perform listed belowfunctions.

The PCBB counts all rising edges of f_(F1) clocks.

When PCBB(9) goes high, the PCBB generates SEL9 signal. The SEL9activates RD_REQ which initiates the PPU to read PCBA via CNTR(15:0).

The PPU calculates an approximate phase error of previous fr_(S2) versusf_(F1), by subtracting from the newly read PCB, the number N of f_(F1)clocks which nominally should correspond to the frame fr_(S2).

When CTRB(14) goes high, the PCBB generates SEL14 signal. The SEL14activates RST_PCBA which initiates PCBA reset circuits after its contenthas been read by PPU.

When fr_(S2) rise occurs, PRESTOP_FF is set to 1 and inverts STOPA/STOPBsignals.

When STOPB signal is active all the above functionality is fulfilledwith reversed roles of STOPB and PCBA versus STOPA and PCBB.

High resolution extension of phase measurements is explained below.

The high resolution extension enhances phase detection resolution to asingle inverter delay i.e. by ˜10 times compared with conventionalmethods based on clock counting. The high resolution measurement isimplemented in the HRPD Config.1, by using the phase capture register(PCR) to measure a positioning of the last rising edge of the secondsignal frame fr_(S2) versus the f_(F1) clock waveform

The phase capture register captures a state of outputs of multipleserially connected gates which the first signal clock f_(F1) iscontinuously propagated through, at the leading edge of the secondsignal frame fr_(S2).

PCR decoders are used in the high resolution extension, and they aredefined below.

The last rise decoder (LRD) provides binary encoded position of f_(F1)rising edge, which has been captured at the most right location of thePCR.

The cycle length decoder (CLD) provides binary encoded lengths of thef_(F1) wave, which has been captured between these 2 falling or 2 risingedges of the f_(F1) wave which occurred at the most right locations ofthe PCR.

Captured PCR content is decoded by the last rise decoder and the cyclelengths decoder. Contents of the LRD and the CLD are later transferredto the phase processing unit (PPU).

The above operations are controlled by a Detector Timing Circuit, whichis shown in the FIG. 1.

Timing analysis of the detector timing circuit is shown in FIG. 2 and isexplained below.

The High Clock Region Flip-Flop (HCR_FF) is set to 1, when f_(F1) riseencounters PCR(0) set to 1. The PCR(0) was set to 1, if an fr_(S2) riseencountered f_(F1)=high. Therefore the HCR_FF=1 signals, that fr_(S2)rising edge occurred during the f_(F1)=high halfcycle.

The PCR(1) is set to 1, when an fr_(S2) rise encounters f_(F1)=low.Therefore the PCR(1)=1 signals, that fr_(S2) rising edge occurred duringthe f_(F1)=low halfcycle.

PRESTOP_FF is set to 1, when f_(F1) fall encounters HCR_FF or PCR(1) setto 1.

STOP_FF is reversed, by any rising edge of the PRESTOP_FF. Any STOP_FFswitching causes a reversal of the PCBA/PCBB functions.

The whole PCR is reset by the signal PhaDet_RST. The PhaDet_RST shall begenerated during fr_(S2)=low halfcycle and after contents of the PCRdecoders are read by the phase processing unit.

It shall be noticed that a first f_(F1) rise which occurs after fr_(S2)rise, will encounter unchanged status of the STOP_FF. Thereforepresently active counter will be increased by 1 by the first f_(F1)rise, but it will be freezed when following f_(F1) fall will reverse theSTOP_FF before an arrival of the second f_(F1) rise.

However since STOP_FF reversal was similarly delayed during previousfr_(S2) measurement, presently active counter missed counting one f_(F1)rise at the beginning of the present measurement.

Therefore the counter content needs to be decreased by 1, in order torepresent a correct number of complete f_(F1) cycles which occurredbetween consecutive rising edges of the fr_(S2) frame.

Phase processing method combines the approximate phase measurement andthe high resolution extension into an actual phase measurement of aframe signal.

The phase processing method uses additional terms which are explainedbelow.

Calculated by PPU, measured phase (MEA_PHA) represents the actual phaseerror between fr_(S2) versus the equivalent f_(F1) frame; and consistsof the listed below components.

LRD/CLD is a normalized value of a phase error between fr_(S2) riseversus last f_(F1) rise, as it has been read by the PPU from the LRD andCLD decoders.

Remaining phase error (REM_PHA) is calculated based on the presentmeasurement results, but PPU stores and uses it to correct the nextmeasurement result. The REM_PHA represents a remainder of a presentlycaptured fraction of the f_(F1) period, which needs to be added to thenext phase error measurement.

Subtracted N which is a nominal number of first signal clocks per asecond signal frame; transforms the counted number of f_(F1) cycles perfr_(S2) period, into an approximate phase error between the fr_(S2)versus the f_(F1).

While the LRD/CLD represents a normalized PCR captured extension of theCNTR(15:0) captured phase, and is added to the present MEA_PHA: theremaining phase error between the fr_(S2) and the next f_(F1) riseamounts to (CLD-LRD)/CLD and it is stored as the REM_PHA, in order tomodify next measurement's MEA_PHA.

Therefore:MEA_PHA=REM_PHA+CNTR−1+LRD/CLD−N, REM_PHA=(CLD−LRD)/CLD.

2. HRPD Config.2 based on ring oscillator captured by frame edge

For the approximate phase measurements the HRPD Config.2 uses the samecircuits as the HRPD Config.1.

High resolution extension for the Config.2 has differences versus theConfig.1, which are shown in the FIG. 3 and are listed below:

-   -   instead of using the open ended delay line as a first clock        signal propagation circuit, the ring oscillator which generates        f_(F1) clock in the PLLxL Freq. Multiplier is used as said        propagation circuit;    -   the cycle lengths decoder CLD is eliminated , because a number        of active gates in the ring oscillator is known.

The phase capture register captures the state of outputs of multipleserially connected gates which form the ring oscillator which the firstsignal clock f_(F1) is continuously propagated through, at the leadingedge of the second signal frame fr_(S2).

Since the ring oscillator gates must use lowered power supply, in orderto allow their delays controllability in the PLL configuration: phasedetection resolution will be slightly lower for the Config.2 versus theConfig.1, but it still shall be significantly better when compared withconventional methods limited to clock counting.

The detector timing circuit and the timing analysis are the same for theConfig.2 as for the Config.1 (see FIG. 1 and FIG. 2).

The only difference between a phase processing method of the Config.2versus the Config.1 is: that since ring gates number (RGN) is alwaysknown, the Config.2 does not need to use the cycle lengths decoder andthe CLD can be replaced by a ring gates number (RGN) in the equationscalculating the MEA_PHA and the REM_PHA.

Therefore:MEA_PHA=REM_PHA+CNTR−1+LRD/RGN−N, REM_PHA=(RGN−LRD)/RGN.

3. HRPD Config.3 based on clock signal captured by frame delay lineedges.

For the approximate phase measurements the HRPD Config.3 uses the samecircuits as the HRPD Config.1.

High resolution extension for the Config.3 has differences versus theConfig.1, which are shown in the FIG. 4 and are listed below:

-   -   instead of propagating the f_(F1) clock through a delay line,        the second signal frame is propagated through the delay line,        and outputs of the delay line gates are used to capture the        f_(F1) clock in corresponding bits of the phase capture register        (PCR);    -   the first rise decoder (FRD) is used in the Config.3 instead of        the last rise decoder (LRD) from the Config.1, since the PCR        content represents f_(F1) waveform occurring after a rising edge        of the fr_(S2) frame;    -   a new bit PCR(−1) is added to the PCR, in order to capture        inverted f_(F1) value which was captured in the PCR(1) bit for        the Config.1.

Since non inverting gates must be used in the delay line, resolution isreduced compared with the Config.1, but still is significantly betterthan with conventional methods.

For the detector timing circuits, the HRPD Config.3 uses similarsolutions as the HRPD Config.1: with the exception of using the signalPCR(−1) (see FIG. 5), instead of the signal PCR(1) (see FIG. 1) toenable activation of the PRESTOP_FF by the first falling edge of thef_(F1).

The timing analysis is very similar for the Config.3 (see FIG. 6) as forthe Config.1 (see FIG. 2). The differencies are caused by the fact thatfor the Config.3 parts of waveforms which occur after the rising edgesof the frame signal are captured, and therefore the captured waveformsare shown on the right sides of the arrows indicating appearances of theframe rising edges.

Phase processing method for the Config.3 is explained below.

Since for the Config.3, the PCR and its decoders represent a part of awaveform which occurs after a frame rising edge:

-   -   a content of the FRD divided by the CLD, represents a REM_PHA        value which shall be added to the next measurement,    -   a fraction of the f_(F1) cycle which shall be added to the        present measurement amounts to:        1−FRD/CLD=(CLD−FRD)/CLD.

Therefore:MEA_PHA=REM_PHA+CNTR−1+(CLD−FRD)/CLD−N, REM_PHA=FRD/CLD.

4. HRPD Config.4 based on frame delay line captured by clock signal.

For the approximate phase measurements the HRPD Config.4 uses the samecircuits as the HRPD Config.1.

High resolution extension for the Config.4 has differences versus theConfig.1, which are shown in the FIG. 7 and are explained below.

Instead of propagating the f_(F1) clock through a delay line, the secondsignal frame is propagated through the delay line, and the outputs ofthe delay line gates are captured after any rising edge of the secondsignal frame:

-   -   the first f_(F1) clock captures the frame delay line in the        front phase capture register (FPCR);    -   the second f_(F1) clock captures the frame delay line in the end        phase capture register (EPCR).

A bit FPCR(−1) is used in the FPCR for capturing present value of thesecond signal frame fr_(S2) by the falling edge of the first signalclock f_(F1).

The last frame decoder (LFD) provides a binary encoded position of thefr_(S2) rising edge versus the first following f_(F1) rising, which hasbeen captured on the right side of the FPCR.

The cycle length decoder (CLD) provides a binary encoded lengths of thef_(F1) wave which is calculated as a difference between a number of gatedelays captured in the EPCR versus a number of gate delays captured inthe FPCR.

Detector Timing Circuit for the Config.4 has differences versus theConfig.1, which are shown in the FIG. 8 and are explained below.

FPCR(−1) is used to activate the HCR_FF which enables activation of thePRESTOP_FF, if an fr_(S2) rise occurred during f_(F1)=high condition.

FPCR(0) is used directly to enable activation of the PRESTOP_FF, if anfr_(S2) rise occurred during f_(F1)=low condition.

An inverted PRESTOP_FF is used as active low STOPFN signal: in order topreserve the frame delay line captured in the FPCR by the first f_(F1)clock after a rising edge of fr_(S2). Normally all the rising edges ofthe f_(F1) clock keep capturing the frame delay line in the FPCR, untilthe capturing is inhibited by STOPFN=low. Since STOPFN=low is generatedbetween the first and the second f_(F1) rise after the rising edge offr_(S2), the final content of the FPCR is the delay line captured by thefirst f_(F1) rise.

Similarly an active low STOPEN signal is generated between the secondand the third f_(F1) rise after the rising edge of fr_(S2). SinceSTOPEN=low inhibits further capturing of the frame delay line in theEPCR, the final content of the EPCR is the delay line captured by thesecond f_(F1) rise.

Timing analysis for the Config.4 is shown in the FIG. 9.

The timing diagrams show both capture events: the delay line capturingby the first f_(F1) rise, and the delay line capturing by the secondf_(F1) rise.

The FPCR(−1) is activated before the FPCR(0): if fr_(S2) rise occursduring f_(F1)=high condition and is captured by f_(F1) fall. Similarlythe FPCR(0) is activated before the FPCR(−1): if fr_(S2) rise occursduring f_(F1)=low condition and is captured by f_(F1) rise.

The STOPFN is shown to be activated as STOPFN=low by the f_(F1) fallafter the first f_(F1) rise. Similarly the STOPEN is shown to beactivated as STOPEN=low by the f_(F1) fall after the second f_(F1) rise.

Phase processing method for the Config.4 is defined below.

LFD/CLD is a normalized value of a phase error between an fr_(S2) riseversus the first f_(F1) rise, as it has been read by PPU from the LFDand CLD decoders.

The content of the LFD divided by the CLD, represents a REM_PHA valuewhich shall be added to the next measurement.

A fraction of the f_(F1) cycle which shall be added to the presentmeasurement amounts to:1−LFD/CLD=(CLD−LFD)/CLD.

Therefore:MEA_PHA=REM_PHA+CNTR−1+(CLD−LFD)/CLD−N, REM_PHA=LFD/CLD.

5. HRPD Config.5 based on frame captured by clock delay line.

For the approximate phase measurements the HRPD Config.5; uses the samecircuits as the HRPD Config.1.

High resolution extension for the Config.5 has differences versus theConfig.1, which are shown in FIG. 10 and are explained below.

The Config.5 implements said capture synchronization method:

-   -   by using the gates from G0 to GR to prevent the delay line        outputs from capturing fr_(S2)=high into any PCR bit whenever        the next PCR bit has been set to 1 before;    -   by using the delayed phase capture register (DPCR) to provide        PCR content which is delayed by f_(F1) halfcycle, in order to        assure sufficient pulse duration for PCR input clocks.

For some integrated circuit technologies, PCR flip-flops propagationdelays may be sufficient to provide said required pulse duration.Therefore for such technologies the DPCR is not needed, since an outputof the next PCR bit can be connected directly to an inverter whichprevents delay line output from passing through the gate connected tothe clock input of the current PCR bit.

The outputs of the delay line gates which the f_(F1) clock is propagatedthrough, keep capturing 0s in the PCR for as long as the second signalframe remains low.

When a rising edge of the fr_(S2) appears (see also FIG. 12):

-   -   the fr_(S2) rise is captured in the PCR simultaneously by two        rising edges of the delay line outputs, which are separated by a        number of delay gates which corresponds to f_(F1) cycle;    -   the two rising edges keep propagating along the delay line and        keep capturing fr_(S2)=high in consecutive PCR bits for as long        as encountered PCR bits have proceeding bits not set to 1;    -   in addition to said two rising edges, a third rising f_(F1) edge        enters the delay line from an f_(F1) source and will keep        propagating and capturing fr_(S2)=high until a bit is        encountered which is proceeded by a set to 1 bit.

Therefore:

-   -   the first delay line rising edge will set all the bits starting        from its fr_(S2) detection bit down to the end of PCR;    -   the second delay line rising edge will set all the bits starting        from its fr_(S2) detection bit until it encounters the bit which        follows the fr_(S2) detection bit of the first line rising edge;    -   the third delay line rising edge will set all the bits starting        from the delay line entry until it encounters the bit which        follows the fr_(S2) detection bit of the second line rising        edge.

A bit PCR(−1) is used in the PCR for capturing present value of thesecond signal frame fr_(S2), by the falling edge of the first signalclock f_(F1).

First frame decoder (FFD) provides binary encoded position of thefr_(S2) rising edge versus the last proceeding f_(F1) rising which hasbeen captured on the left side of the PCR as the fr_(S2) detection bitof the second line rising edge.

Cycle length decoder (CLD) provides binary encoded lengths of the f_(F1)wave, which is calculated as a number of gate delays between: thefr_(S2) detection bit of the first line rising edge, and the fr_(S2)detection bit of the second line rising edge.

Since non inverting gates must be used in the delay line, the resolutionis reduced compared with the Config.1, but still is significantly betterthan with conventional methods.

Detector Timing Circuit for the Config.5 has differences versus theConfig.1, which are shown in the FIG. 11 and are explained below.

PCR(−1) is used to activate the HCR_FF which enables PRESTOP_FFactivation, if an fr_(S2) rise occurred during f_(F1)=high condition.

PCR(0) directly enables PRESTOP_FF activation, , if an fr_(S2) riseoccurred during f_(F1)=low condition.

Phase processing method for the Config.5 is explained below.

FFD/CLD is a normalized value of a phase error between an fr_(S2) riseversus the last f_(F1) rise, as it has been read by the PPU from the FFDand the CLD decoders.

The content of the FFD divided by the CLD shall be added to the presentphase measurement.

A fraction of the f_(F1) cycle which shall be added to the nextmeasurement amounts to:1−FFD/CLD=(CLD−FFD)/CLD.

Therefore:MEA_PHA=REM_PHA+CNTR−1+FFD/CLD−N, REM_PHA=(CLD−FFD)/CLD.

6. HRPD Config.6 based on frame captured by ring oscillator.

For the approximate phase measurements, the HRPD Config.6 uses the samecircuits as the HRPD Config.5.

High resolution extension for the Config.6 has differences versus theConfig.5, which are shown in the FIG. 13 and FIG. 14 and are explainedbelow.

Instead of the open ended delay line, the outputs of the ring oscillatorwhich is phase locked to a stable clock, are used to capture a rise ofthe fr_(S2) signal in the PCR.

Since the number of ring oscillator gates and the f_(F1) clock periodare known, a calibration of the gates propagation delays is not neededfor the HRPD Config.6, and the CLD is not needed as well.

Since the calibration is not needed, and the oscillator gates delayscover all the f_(F1) clock period; the PCR can be much shorter, as itneeds to cover only one f_(F1) clock period.

The Config.6 uses PLLxL Freq. Multiplier to provide the ring oscillatorwhich is phase locked to a stable reference clock. Therefore ringoscillator gates are the serially connected gates which the f_(F1) ispropagated through, and are used to capture a rise of the second signalframe. The ring oscillator gates must use lower power supply in order toallow their delays controllability in the PLL configuration.

Therefore, resolution is slightly reduced compared with the Config.5,but still is significantly better than with conventional methods.

The detector timing circuit is the same for the Config.6 as for theConfig.5.

The timing analysis is very similar for the Config.6 as for theConfig.5. The only difference is that the PCR content is much shorter,since only one f_(F1) clock period needs to be captured.

The only difference between the phase processing method of the Config.6versus the Config.5 is: that since ring gates number (RGN) is alwaysknown, the Config.6 does not need to use the cycle lengths decoder andthe CLD can be replaced by the RGN in the equations calculating theMEA_PHA and the REM_PHA.

Therefore:MEA_PHA=REM_PHA+CNTR−1+FFD/RGN−N REM_PHA=(RGN−FFD)/RGN

1. A digital phase detector for measuring a phase skew between a firstsignal frame consisting of a nominal number of first signal clocks and asecond signal frame, wherein: a frame measurement configuration is usedfor counting the first signal clock during every frame of a secondsignal, and for buffering the counted value until it is read by a phaseprocessing unit; a subtracting circuit is used for subtracting thenominal number of first signal clocks from the counted number of thefirst signal clocks, in order to calculate an approximate phase skewbetween the first signal frame and the second signal frame.
 2. A digitalphase detector as claimed in claim 1, wherein: said subtracting circuitpresets a counter of the first signal clocks to zero minus the nominalnumber of first signal clocks before the first clock counting for everysecond signal frame.
 3. A digital phase detector as claimed in claim 1,further comprising: a phase capture register for capturing a state ofoutputs of serially connected gates which the first signal clock ispropagated through, at the leading edge of the second signal frame.
 4. Adigital phase detector as claimed in claim 1, further comprising: aphase capture register for capturing a rise of the second signal frameby multiple outputs of serially connected gates which the first signalclock is propagated through.
 5. A digital phase detector as claimed inclaim 1, further comprising: a phase capture register for capturing astate of outputs of serially connected gates which the second signalframe is propagated through, by the leading edge of the first signalclock.
 6. A digital phase detector as claimed in claim 1, furthercomprising: a phase capture register for capturing a rise of the firstsignal clock, by multiple outputs of serially connected gates which thesecond signal frame is propagated through.
 7. A digital phase detectoras claimed in claim 3 or in claim 4 or in claim 5 or in claim 6, whereinthe digital phase detector comprises: an open ended line of seriallyconnected components which are used as the serially connected gates. 8.A digital phase detector as claimed in claim 7, wherein the digitalphase detector comprises a calibration method of gates propagationdelays, wherein: a number of the serially connected gates whichrepresents a number of half cycle times of the first signal clock, iscaptured in the phase capture register; the number of half cycle timesof the first signal clock, is divided by the captured number.
 9. Adigital phase detector as claimed in claim 8, wherein the calibrationmethod comprises: a statistical averaging of a result of thecalibration, in order to eliminate most of a granularity error caused bycapturing of an integer and to reduce an error caused by a power supplyripple.
 10. A digital phase detector as claimed in claim 9, wherein thecalibration method further comprises: assigning higher weights for thecaptured number of gates, if the captured number is provided by seriallyconnected gates which are located at the front of the delay line; usingthe weighted cycle gate numbers for the statistical averaging of thecalibration result.
 11. A digital phase detector as claimed in claim 3or in claim 4 or in claim 5 or in claim 6, wherein the digital phasedetector comprises: a ring oscillator which gates are used as theserially connected gates.
 12. A digital phase detector as claimed inclaim 3 or in claim 4 or in claim 5 or in claim 6, wherein the digitalphase detector comprises: a delay locked loop which gates are used asthe serially connected gates.
 13. A digital phase detector as claimed inclaim 3 or in claim 4 or in claim 5 or in claim 6, wherein: a content ofthe phase capture register is used to calculate a phase skew differencebetween the last rise of the first signal clock and the beginning of anew second signal frame; a content of the phase capture register is usedto calculate a remaining phase skew between the beginning of a newsecond signal frame and the first rise of the first signal clock.
 14. Adigital phase detector as claimed in claim 13, wherein: the phase skewdifference is added to the present measurement of a phase skew betweenthe first signal and the second signal, wherein the present measurementapplies to the present frame period of the second signal; the remainingphase skew is added to the next measurement of a phase skew between thefirst signal and the second signal, wherein the next measurement appliesto the next frame period of the second signal.
 15. A digital phasedetector as claimed in claim 13, wherein: the remaining phase skew iscalculated as equal to the first signal clock period minus the phaseskew difference.
 16. A digital phase detector as claimed in claim 13,wherein: a content of the phase capture register is used to upgrade thecounted number of first signal clocks to an actual number of firstsignal clocks which really occurred during the second signal frame. 17.A digital phase detector as claimed in claim 3 or in claim 4 or in claim5 or in claim 6, wherein the digital phase detector comprises: a firstphase counter buffer for counting first signal clocks during every oddcycle of the second signal frame, and for buffering the counted clocksnumber during every following even cycle of the second signal frame; asecond phase counter buffer for counting first signal clocks duringevery even cycle of the second signal frame, and for buffering thecounted clocks number during every following odd cycle of the secondframe; a detector timing circuit for switching the counting and thebuffering functions of the first and the second phase counter buffer.18. A digital phase detector as claimed in claim 17, wherein: theswitching performed by the detector timing circuits is driven by thefirst signal clock and is conditioned by a content of the phase captureregister.
 19. A digital phase detector as claimed in claim 17, wherein:the phase capture register and some of the flip-flops of the detectortiming control, are reset outside of a close time range which surroundsa rising edge of every second signal frame.
 20. A digital phase detectoras claimed in claim 17, wherein: if a rising edge of the second signalframe encounters a high level of the first signal clock, the secondfalling edge of the first signal clock will reverse the counting and thebuffering functions of the first and the second phase counter buffer; ifa rising edge of the second signal frame encounters a low level of thefirst signal clock, the first falling edge of the first signal clockwill reverse the counting and the buffering functions of the first andthe second phase counter buffer.
 21. A digital phase detector as claimedin claim 17, wherein the detector timing circuit comprises a functionswitching flip-flop, wherein: the function switching flip-flop switchedto 1, inhibits counting in the first counter buffer and enables countingin the second counter buffer; the function switching flip-flop switchedto 0, inhibits counting in the second counter buffer and enablescounting in the first counter buffer.
 22. A digital phase detector asclaimed in claim 1, the digital phase detector comprising: a first phasecounter buffer for counting first signal clocks during every odd cycleof the second signal frame, and for buffering the counted clocks numberduring every following even cycle of the second signal frame; a secondphase counter buffer for counting first signal clocks during every evencycle of the second signal frame, and for buffering the counted clocksnumber during every following odd cycle of the second frame.
 23. Adigital phase detector as claimed in claim 22, wherein the digital phasedetector comprises: a detector timing circuit for controlling thecounting and the buffering functions of the first and the second phasecounter buffers.
 24. A digital phase detector as claimed in claim 22,wherein said detector timing circuit further comprises: detection of abeginning of a cycle of the second signal frame; switching the counterbuffers into the counting and buffering operations; requesting the phaseprocessing unit to read the buffered count numbers.
 25. A digital phasedetector as claimed in claim 22, wherein: the first counter buffer isreset after its content is read by a phase processing unit; the secondcounter buffer is reset after its content is read by the phaseprocessing unit.
 26. A digital phase detector as claimed in claim 22,wherein: the first counter buffer is preset to zero minus the nominalnumber of first signal clocks, after its content is read by the phaseprocessing unit; the second counter buffer is preset to zero minus thenominal number of first signal clocks, after its content is read by thephase processing unit.
 27. A digital phase detector as claimed in claim22, wherein the digital phase detector further comprises: a detectortiming circuit for switching the counting and the buffering functions ofthe first and the second phase counter buffer.
 28. A digital phasedetector as claimed in claim 27, wherein the detector timing circuitfurther comprises a function switching flip-flop, wherein: the functionswitching flip-flop switched to 1, inhibits counting in the firstcounter buffer and enables counting in the second counter buffer; thefunction switching flip-flop switched to 0, inhibits counting in thesecond counter buffer and enables counting in the first counter buffer.29. A digital phase detector as claimed in claim 28, wherein the digitalphase detector further comprises: a phase capture register for capturinga state of outputs of serially connected gates which the first signalclock is propagated through, at the leading edge of the second signalframe; an open ended line of serially connected components which areused as the serially connected gates.
 30. A digital phase detector asclaimed in claim 28, wherein the digital phase detector furthercomprises: a phase capture register for capturing a state of outputs ofserially connected gates which the first signal clock is propagatedthrough, at the leading edge of the second signal frame; a ringoscillator which gates are used as the serially connected gates.
 31. Adigital phase detector as claimed in claim 28, wherein the digital phasedetector further comprises: a phase capture register for capturing arise of the first signal clock, by multiple outputs of seriallyconnected gates which the second signal frame is propagated through; anopen ended line of serially connected components which are used as theserially connected gates.
 32. A digital phase detector as claimed inclaim 28, wherein the digital phase detector further comprises: a phasecapture register for capturing a state of outputs of serially connectedgates which the second signal frame is propagated through, by theleading edge of the first signal clock; an open ended line of seriallyconnected components which are used as the serially connected gates. 33.A digital phase detector as claimed in claim 28, wherein the digitalphase detector further comprises: a phase capture register for capturinga rise of the second signal frame by multiple outputs of seriallyconnected gates which the first signal clock is propagated through; anopen ended line of serially connected components which are used as theserially connected gates.
 34. A digital phase detector as claimed inclaim 28, wherein the digital phase detector further comprises: a phasecapture register for capturing a rise of the second signal frame bymultiple outputs of serially connected gates which the first signalclock is propagated through; a ring oscillator which gates are used asthe serially connected gates.
 35. A digital phase detector as claimed inclaim 29 or in claim 30 or in claim 31 or in claim 32 or in claim 33 orin claim 34, wherein: a content of the phase capture register is used tocalculate a phase skew difference between the last rise of the firstsignal clock and the beginning of a new second signal frame; a contentof the phase capture register is used to calculate a remaining phaseskew between the beginning of a new second signal frame and the firstrise of the first signal clock; a high resolution extension iscalculated by adding the remaining phase skew of the previousmeasurement to the phase skew difference of the present measurement; ahigh resolution frame skew is calculated by adding the approximate frameskew to the high resolution extension.
 36. A digital phase detector asclaimed in claim 29 or in claim 30, wherein: bit 0 of the phase captureregister is set to 1, if a rising edge of the second signal frameencounters a high level of the first signal clock; bit 1 of the phasecapture register is set to 1, if a rising edge of the second signalframe encounters a low level of the first signal clock; if the bit 0 isset to 1, it enables a second falling edge of the first signal clock toreverse the function switching flip-flop; if the bit 1 is set to 1, itenables a first falling edge of the first signal clock to reverse thefunction switching flip-flop.
 37. A digital phase detector as claimed inclaim 31, wherein: bit 0 of the phase capture register is set to 1, if arising edge of the second signal fame encounters a high level of thefirst signal clock; bit −1 of the phase capture register is set to 1, ifa rising edge of the second signal frame encounters a low level of thefirst signal clock; if the bit 0 is set to 1, it enables a secondfalling edge of the first signal clock to reverse the function switchingflip-flop; if the bit −1 is set to 1, it enables a first falling edge ofthe first signal clock to reverse the function switching flip-flop. 38.A digital phase detector as claimed in claim 32 or in claim 33 or inclaim 34, wherein: bit −1 of the phase capture register is set to 1, ifa falling edge of the first signal clock encounters a high level of thesecond signal frame before a rising edge of the first signal clock does;bit 0 of the phase capture register is set to 1, if a rising edge of thefirst signal clock encounters a high level of the second signal framebefore a falling edge of the first signal clock does; if the bit −1 isset to 1, it enables a second falling edge of the first signal clock toreverse the function switching flip-flop; if the bit 0 is set to 1, itenables a first falling edge of the first signal clock to reverse thefunction switching flip-flop.
 39. A digital phase detector as claimed inclaim 1, wherein: said first clock counting is enabled by opening alogical gate which controls an application of the first clock to aclocking input of a first clock counter; said first clock counting isdisabled by closing a logical gate which controls an application of thefirst clock to the clocking input of the first clock counter.